----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    04:50:47 02/19/2010 
-- Design Name: 
-- Module Name:    new_demo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity new_demo is
	Port(IMG0_I2C_Clk : out std_logic;
			IMG0_I2C_Data : out std_logic;
		 IMG0_Data : in std_logic_vector(9 downto 0);
		 IMG0_PIXEL_Clk : in std_logic;
		 IMG0_ROW_EN : in std_logic;
		 IMG0_VSYNC : in std_logic;
		 IMG0_RST : out std_logic;

		 IMG1_I2C_Clk : out std_logic;
		 IMG1_I2C_Data : out std_logic;
		 IMG1_Data : in std_logic_vector(9 downto 0);
		 IMG1_PIXEL_Clk : in std_logic;
		 IMG1_ROW_EN : in std_logic;
		 IMG1_VSYNC : in std_logic;
		 IMG1_RST : out std_logic;

		 OEM_I2C_Clk : inout std_logic;
		 OEM_I2C_Data : inout std_logic;
		 OEM_Data : out std_logic_vector(9 downto 0);
		 OEM_PIXEL_Clk : out std_logic;
		 OEM_ROW_EN : out std_logic;
		 OEM_VSYNC : out std_logic;

		 Clk_100MHz : in std_logic;

			  SW : in std_logic_vector(3 downto 0);
			  LED : out std_logic_vector(3 downto 0)
			  );
end new_demo;

architecture Behavioral of new_demo is

begin

	OEM_I2C_Data<='1';
	OEM_I2C_Clk<='Z';
	OEM_Data<=(others=>'0');
	OEM_PIXEL_Clk<='0';
	OEM_ROW_EN<='0';
	OEM_VSYNC<='0';
	
	IMG1_RST<='1';
	IMG0_RST<='1';
	
	IMG1_I2C_Clk<='Z';
	IMG1_I2C_Data<='Z';
	
	IMG0_I2C_Clk<='Z';
	IMG0_I2C_Data<='Z';
	
	LED<="0000";

end Behavioral;

